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Well ok, this idea is strange ;)
What I request would be an possibility to convert a GPX track (say a motorbike) to some line/paths objects in the scene coordinate system, that can be used later on, t…
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## Expected Behavior
LVS should match for SPICE netlist and GDS.
## Actual Behavior
It ain't.
## Steps to Reproduce the Problem
First extract netlist with `magic`.
`netgen -batch lvs…
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I need to modify gate level netlists by changing the input and output of individual gates. Currently, I'm doing this using PCRE. This is an inelegant and haphazard solution. I'd like to instead man…
nblei updated
3 years ago
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can u give more examples about how to use all the functions of tinygarble, like compare, sum, aes, etc
i run the hamming example, and get the right result. but when i run compare, bob always get …
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@ra3xdh
Qucs-S displays ngspice errors and halts even when the netlists sent via DuSpice to ngspice work.
In the attached two projects the following occurs:
Ngspice started...
Error opening …
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## Expected Behavior
Then functional Verilog netlists should compile without any errors.
## Actual Behavior
QuestaSim spits the following error:
_skywater-pdk/libraries/sky130_fd_sc_hd/latest/…
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After updating my system from FreeBSD 13.3 to 13.4, newly compiled parallel Xyce fails all regression tests with illegal instruction errors. This happens even in "parallel build/serial run" mode, whi…
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Hey everyone,
I'm always frustrated when dealing with verilog netlists, that have buses as inputs. HAL does not allow me to write a verilog netlist, that has module inputs or outputs with a certain b…
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I was simulating the transistors in the IHP open PDK, more specific the NMOS and PMOS LV. I was very unsatisfied with the curves, specifically for the intrinsic gain. They were suggesting poor perform…
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**Description**
I'm trying to synthesize a FIFO with ghdl-yosys-plugin for an ice40 device. I don't use explicitly any RAM cell but GHDL+Yosys seems to detect one from an array of ```std_logic_vector…