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When trying to synthesize Lattice SERDES Eye Demo for Versa 5G demo using yosys/nextpnr/prjtrellis tools, I face several issues:
Error: Module 'DCUA' referenced in module 'test1' in cell 'DCU0_inst' …
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[RegFileLoad.v](https://github.com/B-Lang-org/bsc/blob/ae7084d92b8528a9c2b3c4f62f659d533859d0cb/src/Verilog/RegFileLoad.v#L14) does not seem to map to Embedded Block Ram blocks on Lattice ECP5 FPGA (s…
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I seem to be having an issue where when I attempt to use Yosys to synthesis block memory, namely the SP16KD 18K block for the ECP5, it instead defaults to the DPR16X4 distributed RAM instead.
I hav…
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Hi guys,
I'm working on flashspi and board ECPIX5. I had first an issue with specific clock pin as described here: https://github.com/YosysHQ/prjtrellis/issues/158
I finished by just removing th…
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I've run `make` and it failed to build with this error:
```
2.49. Printing statistics.
=== top ===
Number of wires: 89
Number of wire bits: 715
Number of …
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hello!
I have a simple SoC design (a [nerv](https://github.com/YosysHQ/nerv) CPU with some memory and IO), and I am targeting the ECP5 development board. The issue I am getting is device utilizatio…
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Hi All
Please tell me how to resolve this in ubuntu 20.04, I already pip install it. thanks
```
home/peter/workspace/nextpnr>pip install pytrellis
Requirement already satisfied: pytrellis in…
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When trying to configure a ECP5 with an encrypted bitstream I get the following error:
```
simon@simon-VirtualBox:~/Schreibtisch/openFPGALoader_zeugs$ openFPGALoader -c ft2232 /home/simon/Schreibtis…
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Hello,
I have followed the installation instructions for Trellis. I planned to use it with the ECP5 Evaluation Board from Lattice Semiconductor.
I already use the IceStorm toolchain on my system f…
saahm updated
2 years ago
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## Steps to reproduce the issue
I have a true dual port block ram module as generated by the clash-compiler:
```
/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE.
** GENERATED BY CLASH 1.6.…