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I got the following warnings when reading a design checkpoint (attached) generated from another flow (that was created using ModuleInst)
>...WARNING: Hierarchy information reference to non-existent…
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My code is as follows.
```java
public static void main(String[] args) throws FileNotFoundException {
Design design = Design.readCheckpoint("socket_cc.dcp", "socket_cc.edf");
EDIFNetlist …
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According to the [documentation](https://github.com/rachelselinar/DREAMPlaceFPGA/blob/main/IFsupport/README.md) of DREAMPlaceFPGA, before placing the design using DREAMPlaceFPGA, it has to generate th…
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I would like to know if it is possible to relocate a design that contains some encrypted cells (e.g., floating point IP).
For example, I have the following minimal code derived from my project
`…
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See discussion in #351
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Line 786 in bfasst is breaking the weekly error injection CI. However, the same unit tests pass. The issue is most likely to be with designs that are part of the error_injection weekly test but not pa…
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Hi,
I meet an annoying issue when running it.
I run it on Linux, and I can run "vivado" in command.
But in log file, it seems like no founding vivado, I think it is a environment issue.
How can I …
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I am attempting to import a placed design into RapidWright and create a new "cloned" circuit that contains the same placed cells and nets. The imported design has a few placed LUT5-LUT6 pairs. However…
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Hi. For the default RWRoute flow, when we try to run the "report_route_status" for routed design -- "rosetta_fd", we see the following report in the Tcl console of Vivado, showing 2270 nets with routi…
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I keep having the error message,can't read "io_pin_sites": no such variable, while executing 030-iob18 fuzzer.
So, I looked into generate.tcl in 030-iob18 directory.
And I opened my Vivado 2017.2 …