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Using Vivado 2019.2, it seems like the PCIe block name has changed from pcie4c_uscale_plus to pcie4_uscale_plus, so the build fails during the IP generation until this is manually changed (still waiti…
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Hi Brian,
Thanks for your great tutorials! I wanted to alert you to a problem I just encountered, in case others experience similar...
I was compiling (build.sh) and trying to run part-1 / ar…
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Hi,
since I don't see any way to test the complete system performance using the current release v1.8.2 (i.e. no support for remote procs / unknown gpu support ).
Could you please advise on how to …
flpm2 updated
3 years ago
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_From @hartytp on [2017-08-16 05:24](https://github.com/sinara-hw/sinara/issues/253)_
I've started sketching out requirements for a fast DAC to be used for ion shuttling/splitting. It's on the [Wiki…
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This issue serves to track the port to the RISC-V architecture. There is an out-of-tree port at https://github.com/riscv/riscv-go based on Go 1.8 which - according to riscv/riscv-go#19 - is no longer …
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I have been having a look at the performance of Artiq on Zynq SOCs (2x ARM CPU + Artix/Kintex fabric). I am particularly interested in:
* the level of friction / mess in porting to Zynq
* the potent…
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Hello, when I boot with SD card, the board cannot boot Linux, and it displays some errors like this
the first part
```
[ 10.166214] 9pnet: Installing 9P2000 support
[ 10.171324] Key type dns_r…
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* Before opening a new issue, we wanted to provide you with some useful suggestions (Click "Preview" above for a better view):
* Consider checking out SDK [examples](https://github.com/IntelRea…
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Hi, do you have any plan to add the ultrascale-plus Kintex FPGA in example design? such as KCU116.
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A new Kasli based on the forthcoming v1.2 design, but with a Zynq-7000 series FPGA (2x ARM CPU) instead of an Artix-7 (no hard CPU).
This will allow the proposed [Zynq version of Artiq](https://git…