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sinara-hw
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Kasli-SOC
Xilinx ZynQ(R) version of Kasli FPGA controller.
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12V input short circult
#81
IamTaoChen
opened
4 months ago
5
Add P12V0 switch for EEMs
#80
marmeladapk
opened
5 months ago
1
bootloader switch
#78
gkasprow
opened
11 months ago
0
ftdi serial number
#77
jbqubit
closed
11 months ago
3
DIOT(CPCI) version of Kasli SOC
#76
gkasprow
opened
11 months ago
5
EEM8 and EEM9 collide with rails
#75
jordens
opened
1 year ago
2
Undefined behavior with SPI devices on several EEM ports
#74
thomasfire
closed
1 year ago
5
Changelog v1.1.1
#73
maciejprzybysz
opened
1 year ago
0
Add another EEPROM to SHARED_I2C
#72
filipswit
opened
1 year ago
1
replace tantalum caps with ceramic + resistor
#71
dhslichter
opened
1 year ago
0
revision ID and variant ID
#70
gkasprow
closed
1 year ago
1
changelog v1.1
#69
filipswit
opened
1 year ago
25
LDO instable - input capacitance to low
#68
mkiepiela
closed
1 year ago
5
mechanical issues v1.0.1
#67
filipswit
closed
1 year ago
1
parts availability
#66
gkasprow
closed
1 year ago
0
v1.1
#65
jordens
closed
2 years ago
13
PCA9547BS as population option
#64
sbourdeauducq
closed
2 years ago
2
Question about drill holes for the front panel
#63
HarryMakes
closed
2 years ago
3
IC40 label overlaps the copper pad
#62
HarryMakes
closed
2 years ago
3
Track width inconsistency
#61
HarryMakes
closed
2 years ago
1
Typo: incorrect MPN and description for Zynq-7000
#60
HarryMakes
closed
2 years ago
1
Stock problems
#59
pkozakiewicz
closed
2 years ago
5
PHY address
#58
gkasprow
closed
2 years ago
0
I2C switch IC15 not working
#57
sbourdeauducq
closed
3 years ago
2
review T21 gate pulldown
#56
sbourdeauducq
closed
2 years ago
1
master issue: Kasli-SoC v1.0 testing
#55
sbourdeauducq
closed
2 years ago
9
install J24 jumpers (USB SRST + POR) during production
#54
sbourdeauducq
closed
1 year ago
3
Ethernet PHY reset may need to be asserted during power up
#53
sbourdeauducq
closed
2 years ago
5
Fan connector too close to PCB edge
#52
kaolpr
closed
2 years ago
5
Si549 part numbers
#51
pkozakiewicz
closed
2 years ago
1
SFP / USB Chassis connection
#50
kaolpr
closed
2 years ago
1
Rear power connector
#49
kaolpr
closed
3 years ago
2
Add 220pF capacitor between OUT and FB of TPS7A7200
#48
marmeladapk
closed
3 years ago
0
Add testpoints to check power supply voltages
#47
marmeladapk
closed
3 years ago
0
PGOOD is pulled up to 12V while max voltage is 3,3V
#46
marmeladapk
closed
3 years ago
0
Change project settings for pin swapping
#45
marmeladapk
closed
3 years ago
0
Add additional filtering on P12V0 input to buck
#44
marmeladapk
closed
3 years ago
0
Add testpoints on PL UART
#43
marmeladapk
closed
3 years ago
0
Connect EN of IC22 to BDBUS6
#42
marmeladapk
closed
3 years ago
0
SD_DET should be pulled up with 50k
#41
marmeladapk
closed
3 years ago
0
Add pullups to 2V5 JTAG signals
#40
marmeladapk
closed
3 years ago
0
IC41 is way to close to Si549 oscillators
#39
marmeladapk
closed
3 years ago
1
R37 and R225 should be 0 when LVDS version of Si549 is placed
#38
marmeladapk
closed
3 years ago
0
Increase P3V6_CLK voltage
#37
marmeladapk
closed
3 years ago
1
No title on bank500-501 sheet
#36
marmeladapk
closed
3 years ago
0
Incorrect variant link warning when compiling project
#35
marmeladapk
closed
3 years ago
0
Missing file from project
#34
marmeladapk
closed
3 years ago
0
speed grade
#33
sbourdeauducq
closed
3 years ago
3
machine-readable FPGA pin definition files
#32
sbourdeauducq
closed
3 years ago
1
compare with kasli 2.1
#31
hartytp
opened
3 years ago
5
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