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I have been looking to add support for Windows but hit a few brick walls. I'm looking for advice on the best way to do that for the project, assuming supporting Windows is desired of course!
I look…
corco updated
2 years ago
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### Problem description
This seems to be a rehash of https://github.com/williamboman/nvim-lsp-installer/issues/350 which I believe https://github.com/williamboman/nvim-lsp-installer/pull/352/files fi…
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my command is “ ./verible-verilog-format --assignment_statement_alignment=align --named_parameter_alignment=align --class_member_variables_alignment=align --formal_parameters_indentation=wrap tb.sv”
…
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We're presumably doing this because then it passes lint, but it adds a burden on contributors to have the right version of `clang-format` (and maybe Verible in the future), even if they're not directl…
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**Test case**
```systemverilog
module foo;
bar#(
.param_a(1)
// pragma synthesis off
,
.param_b(2)
// pragma synthesis on
) m_bar ();
endmodule
```
Runnin…
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**Describe the bug**
An empty generate block is labelled as a syntax error. ~~This also seems to apply with generate blocks with more syntax inside of them, but this is the simplest case that repro…
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@gmartin102 noticed a number of other places where the width is hardcoded [19:0]. They should probably be fixed to be `APB_FPGA_ADDR_WIDTH` also. Please @gmartin102 if you could address that in a sepa…
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**Test case**
```systemverilog
module foo();
initial wait (a == b);
endmodule
```
According to the style-guide we use, the keyword `wait` should have spaces around
https://github.com/lowR…
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I moved `VHDLVersion` to pyVHDLModel. See https://github.com/VHDL/pyVHDLModel/pull/29.
I would like to kickout `VerilogVersion` and `SystemVerilogVersion` as well to a `pySystemVerilogModel` reposi…
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**Describe the bug**
This was discovered by me being unable to properly read the documentation.
```
Additionally, the --rules_config flag can be used to read configuration stored in a file. The…