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Following the tutorials, it is only clear how to interface with the DDR directly through the ShimDMA in [tutorial 5](https://github.com/Xilinx/mlir-aie/tree/main/tutorials/tutorial-5), i.e. from L1 di…
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We've been trying to compile RecoNIC and were under the impression that it required the ErNIC IP but not the P4 IP. We have obtained an ErNIC license and it is active for our install of Vivado/Vitis.
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Hello,
I had an issue with Vitis and I finally found a fix. Since I don't really know where to share it for other people, I found that here could be a good place.
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**Issue**:
- Open viv…
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Hi,
I came across your design as I am looking for a Ethernet design with UDP listener to be implemented on FPGA. I have a Alveo u50 card installed in my machine. I was able to generate the bitstrea…
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Hi, I am trying to map an application from Vitis HLS to TAPA. The design almost fully streaming, but there are some parts where I need ping-pong buffer behavior. Is this currently supported by TAPA?
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Hi,
I got the following output when reading the attached design checkpoint
>==============================================================================
== Reading DCP: soc…
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On up-to-date main branch, running from within this docker [image](https://github.com/cmu-sei/hls4ml-docker/blob/main/Dockerfile)
Attempting to synthesize hls from ONNX model. First, I ran python c…
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@xerpi has been working a Halide (to MLIR) to Calyx flow and we should give it a try and get a sense of what we need to do to support it.
Some information from on this (courtesy @xerpi):
* CIRCT b…
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I have the following model:
```
x_in = Input(shape=(1024,1,2))
x = Permute((3,1,2))(x_in)
x = Conv2D(8 , (7,1), padding='same', name='C1')(x)
x = ReLU(name='C1_relu')(x)
x = Conv2D(16, (7,1), …