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时序的课
【FPGA开发中xilinx vivado 平台时序分析系列课程-更新至15讲】 https://www.bilibili.com/video/BV197411G7zS/
下面有几个链接 抵制熊那个课可以看看
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For exemple, Xilinx and Altera have their own file format to specify mapping between design pins and package pins (+ specify pin technologies, current, terminaison, ...)
It could be great to have a s…
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One of the basic ideas of QNICE-FPGA is, that it is meant to be highly portable. For sure we are not there, yet ;-)
Currently, everything is quite Xilinx specific.
* Right now, we have two hardw…
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Vitis AI version: 1.4
System: Ubuntu 16.04
GPU: NVIDIA GeForce RTX 2080 SUPER
I want to speed the quantization process, so I tried to install the Vitis AI 1.4 on my computer with Ubuntu 16.04, wh…
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I am trying to generate elf file from .pb(Tensorflow model) file for xilinx zcu104 board. If you have the proper steps and flow can you please share the same.
Thanks,
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Hi Jeff,
Looks like Xilinx must have changed the name of the PS reset block in the netlist. In order for this project to successfully build, you need to replace all instances of `*rst_ps7_0_100M*` …
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Hi,
the format specifier %08x causes some troube when building for 64bit machines.
`xilinx/netif/xadapter.c:187:44: warning: format '%x' expects argument of type 'unsigned int', but argument 2 h…
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之前装了Vivado2020.2，现在需要装2017.1，是从博客园看的攻略，怕博客园倒闭了，在这里记录一下
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I'm not sure if this is intended or if I'm missing something, but this line:
https://github.com/strezh/XPDMA/blob/master/driver/xpdma_driver.c#L337
Only looks like it would work when direction i…
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Hello!
Where can I get dnndk v2.06 library as links to deephi.com not works anymore?