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When working with VHDL designs, it's common to have constants defined in packages for use across many source files. At the moment, the only way to access those constants is to create copies in the dut…
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Hi @michaelgmcintyre ,
While trying to implement this project in Vivado, we found some syntax errors and some ports which were wrongly declared, like in file:
- [ ] https://github.com/opencomputepro…
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**Bug description**
Linting of a verilog file produces the error _Cannot read property 'logger' of undefined_.
As far as I can tell this isn't limited to modelsim, but I only have modelsim installed…
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Currently, metadata pertaining to grammars and case-by-case exceptions are handled in four different places:
* [`.gitmodules`](https://github.com/github/linguist/blob/b7f579597050aaf7ac19c6c6ec5042…
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Currently, the performance of uniquification and namespace insertion/queries for vectors is pretty bad. The vectors are flattened into the namespace.
Consider:
```
foo: UInt[4]
```
For a na…
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I attempted to convert this project to Verilog so I could use it in Xilinx ISE.
I used a utility called sv2v (https://github.com/zachjs/sv2v).
I had to change 3 wires to reg after conversion and the…
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Type: Bug
### Issue
Setting Update: Mode to `none` in the VS Code settings will inadvertently cause the application to update anyways if the latest update has already been downloaded.
### Expec…
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This is the continuation of the discussion started at the end of #15.
@bschn2 you make a good point indeed. However then what can be done is to compute a pre-hash of the whole initial message used …
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Currently, a `let` declaration in a case item without block like below can be parsed and veryl report a `latch generation` error.
```
// module definition
module ModuleA (
i_sel : input log…
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I've noticed that ppx_deriving_yojson has a far more comprehensive testsuite than the other plugins. I think it might be useful if all the various plugin authors contributed to a shared testsuite tha…