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fx68k
FX68K 68000 cycle accurate SystemVerilog core
GNU General Public License v3.0
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SystemVerilog to Verilog conversion seems to be successful
#16
Willyarma
opened
3 weeks ago
3
Is BGACKn behavior correct?
#15
tcdev42
closed
6 months ago
4
Warnings by GoWin IDE
#14
harbaum
closed
9 months ago
2
Zolt
#13
Antonkalmyk
closed
1 year ago
1
Usage of synthesis on / off
#12
udif
opened
1 year ago
6
Enumerated value used on its own in if condition
#11
jotego
opened
2 years ago
2
X assignments
#10
jotego
closed
2 years ago
2
subq instruction bug
#9
jotego
closed
3 years ago
2
Optional BRAM-based register file on Altera
#8
gyurco
opened
3 years ago
7
Hidden bug
#7
jotego
closed
3 years ago
15
Core performance and size improvement
#6
fredrequin
opened
3 years ago
14
Add clock enable outputs for the E clock
#5
gyurco
closed
3 years ago
3
How to request the bus?
#4
jotego
closed
3 years ago
6
Possible issue with UNLK
#3
apolkosnik
closed
4 years ago
2
Not compatible with iVerilog
#2
jotego
closed
1 year ago
18
HALT input signal.
#1
srg320
closed
4 years ago
4