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Im using ZEDBOARD for FPGA.
The problem raise when try to generate verilog code from fpga-zynq
im using this version of rocket chip https://github.com/ucb-bar/rocket-chip/commit/255ef05e21b583f3287…
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I am trying to follow the instructions from README.md at "Working with Vivado" chapter to build a vivado project. When I enter **`make project`** command, I run into many build issues. The first issue…
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I want to use multiclock in the rocket-chip project as an FPGA design, with high frequency core and low frequency uncore. I change the `BuildCoreplex` and `BuildExampleTop` as following
```
case …
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I have the following code:
``` scala
class DecodeUnitIo(implicit p: Parameters) extends BoomBundle()(p)
{
// val enq_uop =…
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It would be handy to do this:
```
val slaveWait = Reg(init = Bool(false), next = (io.port.scl.oe && !dSCLOen && !sSCL) || (slaveWait && !sSCL))
```
Unfortunately, it doesn't work:
```
r…
sols1 updated
7 years ago
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Building from a fresh clone using the instructions in the readme gives the following error
(Reproduced on two different platforms)
```
[info] Set current project to rocketchip (in build file:/h…
jsren updated
7 years ago
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There are hardcoded debugrom contents in src/main/scala/uncore/devices/Debug.scala coming from riscv-tools/....
I am thinking how to have an easier update cycle for debugrom. I could set it up to pu…
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This can be observed in `vsim/` with a simple `make -n verilog`. Chisel is run, and then firrtl is run twice with identical arguments.
Presumably there is some bug in `Makefrag-verilog` that is caus…
ben-k updated
7 years ago
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```
[error] /rocket-chip/boom/src/main/scala/tile.scala:20: type mismatch;
[error] found : Chisel.Bool
[error] (which expands to) chisel3.core.Bool
[error] required: Chisel.Clock
[error] …
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I use riscv tools version: 886d8131dbd23533fb04d2d76a80be21d5f9ee7a and riscv-isa-sim version: 53d74f4cc31ecf5bb6499b886d8fcbc992a17920
First I compile `hello.c` with `-g` to `hello.rv`:
```
$ ri…