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I think that the best way to make sure that every single Verilog file is bug-free is to create a test bench for each one. I did this for the logic gates on my old machine, but unfortunately I don't ha…
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Clash 1.6.4 (and 1.6.3) compiled against ghc 8.8.4 on debian unstable synthesizes verilog fine for my code, but 1.6.4 compiled against ghc 9.0.2 fails on the same synthesis. Same machine, same everyth…
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Apparently some of the files are like "abstract base classes" so should be marked as parse only.
Verilator is failing on these because it parses it and then sees the abstract nature and correctly …
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Can you add support for the register description language SystemRDL?
Here is a link to the standard https://www.accellera.org/downloads/standards/systemrdl.
There is also a great open-source commu…
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Hi! The manual suggests that pattern matching on strings ought to be possible. I think sail has probably moved on from the syntax given there, but I can't seem to figure out whether this is still supp…
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Hello!
It appears that after fixing #5472 there was a regression and now the simulation stops after executing the `initial` process even in a `module` block (not only in `program` block).
Expect…
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-I have been trying to enable the core tracer log file to check the instruction execution time, PC, instruction itself, and so on. According to the documentation, I should define CV32E40P_TRACER_EXECU…
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Explicit instantiations of standard cells like this:
```sv
module tc_clk_inverter (
input logic clk_i,
output logic clk_o
);
(* keep *)(* dont_touch = "true" *)
sg13g2_inv_1 i_in…
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What am I doing wrong here?
`Prompt: Missing directory /Users/niv/.nimble/pkgs/neverwinter-1.1.1/src/neverwinter. Continue? [y/N]`
Package in question: https://github.com/niv/neverwinter.nim
…
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Thanks for writing this, I find it really useful. Perhaps you could consider adding this to Package Control for Sublime Text.
https://sublime.wbond.net/