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I want to run LiteX on xilinx_alveo_u200 board.
Since `xilinx_alveo_u200` is not available in LiteX so I have modified from `xilinx_alveo_u250`.
The target file was kept the same as `xilinx_alveo_u2…
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Hi @mariodruiz,
This is following from issue #93. Please let me just reiterate the problem. I'm using a `basic` design on Alveo U280 with one node. In my setup, each node has three interfaces conne…
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Hi,
First, I would like to thank you for such a great repository. My question is that is it possible to run the basic benchmark (vnx-basic.ipynb) in a way that the FPGA and a 100Gb NIC would not be…
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I am currently using the antmicro data center dram tester board, and am trying to get it working with the vexriscv_smp cpu. I was able to run it with the vexriscv successfully. First I ran the command…
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Hello and thanks for your work in this repository. I am using Vivado 2018.3 for the VCU1525 board, is there an easy way to port your board files in the older Vivado version?
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* PYNQ version (e.g. v2.6): 2.7.1
* Board name (e.g. Pynq-Z2): Alveo U280
* Description:
ip_dict is incorrect when multiple memory banks are attached to one kernel AXIMM interface, e.g. for HBM[0…
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* PYNQ version: 2.7
* Board name: Alveo U280
* XRT version: 2.13.399
* Description: When getting a handle to a CU with 64b unsigned int arguments, pynq fails with `KeyError: 'unsigned long long'
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I am trying to get the PointPillars example (`demo/Vitis-AI-Library/samples/pointpillars`) working on the Alveo U280 and Vitis AI 1.4.1.
It seems to me that the model and library were not originall…
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Hello.
I found AU200 files became available a few days ago, so I tried them.
I built a bitstream by command like below, and programed my AU200 using Vivado Hardware Manager.
`litex-boards/litex…
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Thank you for your work!
When I run the command "hls_model.build(csim=False,synth=True, ecxport=True, bitfile=True)" with the newest branch, I met the error “ERROR: [Common 17-69] Command failed: The…