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The AI-ARTIQ laser module header board has an additional voltage sensing stage that goes to another MCU ADC pin. That is a better point for voltage sensing due to https://github.com/sinara-hw/Laser_Mo…
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Hi,
In our lab, we use control systems forked from Sandia National Lab https://github.com/QITI/IonControl and ARTIQ.
I am thinking of adding the capability of sending shots to lyse from our cont…
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## One-Line Summary
Is there anyway to get more than 16 ROIs from the grabber per EMCCD camera frame?
## Issue Details
We have a system that requires us to average around 200 ROIs per camera …
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# Bug Report
## One-Line Summary
After a system powercycle (un- and re-plugging 12 V on Kasli), the first set of Sampler samples are invalid.
## Issue Details
Using the artiq_sina…
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### Feature you want to implement
`DataViewerApp` features:
1. Source selection: Choose the data source among the current experiment (realtime), the result in the artiq-master (remote), the local fi…
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# Question
## Category: Compiler Docs
## Description
https://m-labs.hk/artiq/manual-release-4/compiler.html#pitfalls says that you should be able to run ``round(float(numpy.float64(1.0)))`` t…
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### Summary
A simple experiment that writes frequency, amplitude, and switch state information to two Urukul DDS channels doesn't execute the second write when a long delay (~100ms) is added between …
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At least on Xilinx, an input-only pin have much wider IOStandard compatibility (you can have an LVDS_25 input on a VCCIO=3.3 bank but not an output).
Cleanup (make this less of a hack) https://github…
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# ARTIQ Feature Request
## Problem this request addresses
For now artiq_sinara_tester doesn't have dedicated test process for the LVDS TTL card, which results in need of continuous reflashing th…