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jesd204b
JESD204B core for Migen/MiSoC
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setup: remove tests from output
#15
drewrisinger
closed
3 years ago
1
GTH: Fix QPLL module instantiation & introduce freq(TXUSRCLK)=freq(TXOUTCLK)/2
#14
HarryMakes
closed
3 years ago
2
Nix build includes test directory in $out
#13
drewrisinger
opened
4 years ago
1
Figure out if multiple initialization attempts at startup is the expected behaviour
#12
enjoy-digital
opened
7 years ago
1
Handle the JSYNC pin completely
#11
enjoy-digital
closed
7 years ago
1
clean up parameter management
#10
sbourdeauducq
closed
7 years ago
3
always react to SYNC requests
#9
jordens
closed
7 years ago
5
ditch the elastic buffers
#8
sbourdeauducq
closed
6 years ago
10
License?
#7
caryan
closed
7 years ago
23
transceiver initialization/CGS at 10 GHz
#6
jordens
closed
7 years ago
11
[subclass 1] sample sysref, LMFC, align ILAS to sysref
#5
jordens
opened
7 years ago
7
try replacing phy*_tx BUFGs with BUFH/R/MR
#4
jordens
closed
7 years ago
0
Fix transceiver initialization for high linerates
#3
enjoy-digital
closed
7 years ago
2
use elastic buffers instead of async FIFO
#2
sbourdeauducq
closed
7 years ago
3
QPLL for higher linerates
#1
jordens
closed
7 years ago
2