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Hello, I am a little confused about the bare metal program：
1.CoreAXI4DMAController v2.0 provides two ways to start DMA operations, one is to use the startup register, and the other is to use the STR…
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I think this is the right repository to place this issue, but it could need posting in the casperfpga repository.
When using the ZCU111 with rfdc GUI block, there are some methods of input that lea…
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This is more of a question (or perhaps a feature request) than an issue.
I was reading the [documentation of the wiring module](https://amaranth-lang.org/docs/amaranth/latest/stdlib/wiring.html#) i…
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This may or may not be related. In addition to a receive only antenna (Beverage) that I attach to
port RX2, I also attach a preamplified and multi coupled Shared Apex Loop on Ant Port 3, and my
pri…
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I observed hanging in FPGA when CL continuously wrote to the host memory through PCIM. Each write request contains 512B (awlen=7). The hanging is only observed at 136MHz CL clk, but not observed when …
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Hi, currently testing stuff with the following config :
AXI4 64 bits -> digilent nexys video DDR (16 bits physical, 128 bits access bus)
Things seems to mess up between lower and upper 64 bits of…
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Hi!
As the title states, I am unsure with what project base I should start.
There is quite a palette of different choices:
http://redpitaya.readthedocs.io/en/latest/fpga/fpga.html#fpga-sub-proj…
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Hello,
i created a block design on vivado 2018.3 of Video test pattern generator (v8.0), frame buffer and zynq U+.
i am trying to build petalinux using linux-xlnx tags ( xlnx_rebase_v4.14) and …
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Sysstem: Ubuntu
Vivado: 2017.4 Webversion
after excute make PRJ = calssic
the error code is
ERROR: [Synth 8-439] module 'system' not found [/home/tina/Documents/RedPitaya/fpga/prj/mercury/rtl/red_…