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# [LiteX] QEmu simulation of a LiteX generated SoC
More technical details at [Issue #86: Get lm32 firmware running under qemu to enable testing without hardware on HDMI2USB-misoc-firmware repo](htt…
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I have 2 xilinx targets with MPSOC. multicore arm along side fpga. The 10G ethernet links the targets. This 10G ethernet is xilinx softcore on the fpga portion of SOC(system on chip). I have linux ru…
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it'd be great to be able to optionally use a few GPIO out pins so they can be used for scoping events in-kernel as well as from arbitrary userland code, a bit like i[n this example](https://github.com…
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### Is there an existing core-v-mcu bug for this?
- [X] I have searched the existing bug issues
### Bug Description
In the `rtl/includes/pulp_soc_defines.svh` file [here](https://github.com/o…
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I have had no luck generating a working DDR3 Verilog module for Digilent NexysVideo Artix-7 FPGA using:
```
{
# General ------------------------------------------------------------------
"…
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Hi there, I watched your course "VSD - Mixed-signal RISC-V based SoC on FPGA", and I ran the code under "vsdfpga/verilog", and I just noticed that many verilog files under "vsdfpga/verilog" is generat…
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Smart NICs can potentially help accelerate Gatekeeper's performance. Example of Smart NICs: [Netronome Agilio](https://www.netronome.com/products/smartnic/overview/).
They can be used to [accelerat…
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Hi
I attempted to compile Pulpissimo on ZCU104. It ends up with timing constraints aren't met:
Current Timing Summary | WNS=-7.567 | TNS=-29782.275
The procedure I followed is:
1. download pulpis…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
Red Semi is trying to get Linux running on the Nexys Video build of the CVA soc, and th…
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I get the following error from litex. It seems slightly werid because that is because a `name` is not passed to CSRStorage.
```
lxbuildenv: v2020.6.1.1 (run ./bitstream.py --lx-help for help)
fat…