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Hi there,
I am quite unsure if this issue stems from PyRTL itself and am looking for some feedback/suggestions.
I have a flow where I am doing timing analysis on VHDL code.
`VHDL -> GHDL plug…
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Hi everyone, I would like to write a small tool which, given a VHDL file describing an entity plus its architecture, would allow me to draw its corresponding schematic. It should at least include:
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**Is your feature request related to a problem? Please describe.**
To be more user friendly, PSL assertions could be added to waveform dump (GHW only since FST and VCD).
**Describe the solution yo…
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## Description
Yosys (or is it abc ?) could better optimize logic and arith expressions on LUT-based FPGA architectures.
With the following very low-complexity pass:
When it is very visible tha…
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Currently GHDL is compiled for Windows with MinGW and we can proof it works fine with mcode and llvm backends. Compiling GHDL with GNAT (Ada compiler from Ada Core) is hard to maintain. The current sc…
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**Description**
When trying to synthesize a large design into verilog I run into a GHDL crash. The design I am synthesizing is both complex and large. Synthesis up until the crash used about 85 GiB o…
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@umarcor @LarsAsplund @JimLewis @eine @suzizecat @Paebbels @nfrancque I have been talking a bit with @qarlosalberto about potentially creating a sphinx builder/autodoc plugin for HDL, although I'm mor…
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There is currently little to no coordination between developers/contributors of ghdl and packagers/maintainers of different package managers. After checking the existing packages for fedora and archli…
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**Description**
Definind a 2-dimension array constant whose dimensions are not power of two, the synthesized code is invalid.
**How to reproduce?**
Minimal example:
```vhd :file: ent.vhd
libr…
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By looking at the sources of this repo, it seems that the project is to generate artifacts for a wide range of platforms (both OSs and architectures). That's nice! However, I'm lacking some explanatio…