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In my `caravel_user_project`-derived project I cannot run `make user_proj_example` or even my own design through `make bfg_mux_test`. Both fail with a 'permission denied' error accessing a path in the…
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There is a link just above https://github.com/efabless/caravel_user_project/blob/main/docs/source/index.rst#running-openlane that goes to `https://github.com/The-OpenROAD-Project/OpenLane/blob/master/…
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### Description
I am trying out the Tutorial "Designing a chip with an OpenRAM (sky130)" when I run the command "./flow.tcl -design ./designs/ci/test_sram_macro -tag synthesis_only -to synthesis -ov…
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This is issue might be related to: #518
When reading multiple sv files and running through synthesis in [openlane](https://github.com/msaligane/openlane/tree/use-yosys-uhdm-plugin/designs/opentita…
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Ever since updating the Makefile in my project to the one using the `efabless/openlane:2023.02.14` Docker image, I am unable to build macros above a certain size. After experimenting a bit, the limit …
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@andars
I'm unable to synthesis your RTL and facing following issue during yosys synthesis.
```
12.1. Analyzing design hierarchy..
Top module: \top_4ft4
Used module: \wb_system
Used modu…
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# :wave: Welcome to OpenLane's GitHub Learning Lab "Crash Course in GitHub at OpenLane"
To get started, I’ll guide you through some important first steps in coding and collaborating on GitHub.
Peopl…
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Thank you for your excellent work and the provided dataset.
I have a question regarding the training process of CLRNet and GANet on the OpenLane-V dataset.
I attempted to reproduce the results usi…
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In the sky130A LEF file, for the cell macros, I can see interconnect (li1) layers for pins and power/ground, but the other layers and connections in the final layout aren’t included there. For example…
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Currently we CI seems to only harden the user project macro, it would be nice to also harden the `user_project_wrapper` so that we can also catch regression over the integration with caravel.