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Hello,
I have already integrated NVDLA small and tested on VC707, it works perfect. Now I want to try NVDLA large. It seems one can not integrate NVDLA large by using the guide https://www.esp.cs.col…
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Hello. I saw several projects aiming to integrate softcore to Arduino IDE in a way that the FPGA can then be programmed in C quite easily without much user setup.
For example the lattuino project:
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The simulation with the `riscV (VexRISC) ` cpu is way slower than `swift2`. `Swift2 `is faster more than 4 times. This may be because `riscV (VexRISC) `cpu doesn't have cache memory and it's using `SP…
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Hi, I tried running it with just one tile. While there don't appear to be any errors based on the terminal messages, my perf.log file is still empty. Is this expected behavior, or could there be an is…
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#critical
Hi,
We followed all the steps for RISC-V setup on PYNQ Z2 board. But during the last step, in packaging the overlay, when we tried to run this code
`import numpy as np
arg1 = np.a…
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Hi dear all,
I try to implement picorv32 on PYNQ-Z1 using vivado 2019.2 I followed your instructions until Packaging an Overlay. **Testing the Tutorial Overlay** failed due to the same error mentio…
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The SCons file is quite "magical" and undocumented at the moment. I needed to find it to understand these points for example:
- how is a PCF file located? which is chosen if there are multiple?
- …
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Hi!
As one of the Tillitis developers, I love to see this project.
A possible small improvement I would like to suggest is to use Blake2 when generating random numbers. The TRNG generates quite …
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nextpnr-ice40 operates at the logic cell (LUT+FF) level. Investigate the effect of clustering related logic together to take advantage of any local feedback paths (are there any?) and to reduce the pl…