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FreePDK?
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It would be awesome to see how this CPU would work in ASIC form and Google is offering free tape outs to open source silicon projects on SkyWater's 130nm and GlobalFoundries 180nm MCU process technolo…
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## Expected Behavior
The behavioral/functional Verilog netlists should work in HDL simulation
## Actual Behavior
The behavioral Verilog netlist of High-Density standard cell `stdfrtp` has critica…
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## Expected Behavior
Verilog views shouldn't have any syntax errors.
## Actual Behavior
The behavioral model for the `sky130_fd_sc_hd__dlxbn` has an invalid verilog syntax at `wire 1;`
T…
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Now we have nice [docs](https://gdsfactory.github.io/skywater130/)
Where can I find each standard cell description?
@mithro
@proppy
@RTimothyEdwards
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See https://github.com/google/skywater-pdk-sky130-raw-data/issues/1#issuecomment-1202386286
@miesli inferred that the naming scheme could be something like:
```
sky130_fd_pr__nfet_01v8_w0p36u_l0p…
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I just read https://fossi-foundation.org/2020/06/30/skywater-pdk and thought it might (or might not) be suitable for (parts of) betrusted stuff.
If you already heard of this, please wrap up your th…
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The analog pad (as well as other pads) provided as part of the skywater 130 pdk contains DRC errors
Steps to repoduce:
- Install magic rev. 8.3.399
- Install the skywater pdk using open_pdks rev…
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The PDK currently has auto-generated "test" benches for all the standard cells and models. See the following examples;
- https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd/+/r…
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