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### Description
I have successfully generated GDSII file with open lane for picorv32 with configuration using docker container.
However when I try to get GDSII for Rocket chip with Tiny configuratio…
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### Subject
[Documentation] for documentation errors.
### Describe the bug
Get failures when running design riscv32i and swerv_wrapper with ASAP7 PDK. And flow is OK for designs without hierarchy (…
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### Description
Never completes...
To reproduce(I suppose it should be possible to make a small text only based unit-test that reproduces the problem, but I don't know how to):
unzip https://…
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This is to discuss a strategy for potential model performance improvement. The idea is to use code specialization for quasi static signals. The obvious example is reset, which in the SweRV EH1 testben…
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I am trying to convert a property statement using the [seqprop](https://github.com/zachjs/sv2v/tree/seqprop) branch . I would like to read the converted code with yosys, but I get an error. Can you te…
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I am student that did a research project on open-source implementations of the debugging specification.
What I noticed was that a lacking specification of an interface to the Debug Module resulted …
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### Describe the bug
asap7/swerv_wrapper now ends with one drc:
![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/761514/c4fa502b-9779-45ce-aa26-06aeee16e3d4)
It looks like the c…
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Anybody got any ideas about this?
I was successfully using an OpenOCD build a while ago to run the tests against the SiFive HiFive1 Rev A01:
* https://github.com/riscv/riscv-openocd/issues/869#i…
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INFO: Generating ::swervolf-swerv_el2_arty_a7_config:0.7.4
Can't locate Bit/Vector.pm in @INC (you may need to inst…
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Hi,
I am going to do ASIC of SweRV EL2 for that I am using SRAM as a external memory with a memory controller (axi2mem sram adapter) but I am facing a issue during fetching instruction, core is fetc…