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zachjs
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sv2v
SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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[Feature Request] Copy comments over
#288
Willyarma
opened
1 week ago
1
Non-exhaustive patterns in Part _ _ Module _ name _ _ with --write=DIR option
#287
tarik-ibrahimovic
closed
1 week ago
5
Integration with SVase?!
#286
chili-chips-ba
opened
1 week ago
6
SV2V QA test suite
#285
chili-chips-ba
opened
1 week ago
4
Build fails on MacOS
#284
zaun
closed
1 month ago
2
How to build on GNU/Linux on arm64?
#283
spth
closed
1 week ago
16
How to build on GNU/Linux on ppc64?
#282
spth
closed
1 week ago
9
Test correct and incorrect type parameters from CVA6
#281
jrrk2
opened
2 months ago
3
regarding system verilog to verilog
#280
sundeep2249
opened
2 months ago
8
File name too long
#279
RHamalainen
closed
1 month ago
3
Add support for `disable` statement
#278
spth
opened
3 months ago
4
LLVM dependency
#277
jrrk2
closed
2 months ago
4
Initial support for system tasks
#276
sifferman
opened
5 months ago
7
Automatic Function Produces Construct with Infinite Loop in Yosys
#275
wrs225
opened
5 months ago
4
Added `full_case` and `parallel_case` attributes
#274
sifferman
closed
3 months ago
7
Convert severity tasks to Verilog
#273
sifferman
opened
5 months ago
3
Token '#' issue in wire definition and assignment
#272
stitchlibar
closed
5 months ago
1
Mutidimensional Packed Arrays Handler Does Not Match Commercial Synthesis Tools
#271
sifferman
opened
5 months ago
1
Support for `unique` and `priority`
#270
sifferman
closed
3 months ago
0
Option to Convert Procedural Blocks to Modules
#269
sifferman
closed
4 months ago
0
SV2V automatically removes parentheses in operator precedence
#268
anhdv2000
closed
4 months ago
6
Width extension converts string to int and changes endianess / byte order
#267
vogelpi
closed
6 months ago
2
Converted Verilog Outputs Different Result Compared to Original SysVerilog
#266
marchuang6272
closed
4 months ago
3
Different types in generate branches results in error
#265
mole99
opened
6 months ago
2
fork-join with wait produce a parse error
#264
gggmmm
closed
4 months ago
2
Would you please implement those enum methods for SystemVerilog ?
#263
forthyen
opened
7 months ago
1
Streaming operator is not converted when combined with conditional operator
#262
KatCe
closed
5 months ago
2
`input reg` is not allowed in Verilog
#261
YikeZhou
closed
6 months ago
2
Array literals flow into Verilog unchanged
#260
YikeZhou
opened
7 months ago
0
data type `string` not removed from module item
#259
YikeZhou
closed
4 months ago
4
Unexpected interface mismatch error when using "modport"
#258
YikeZhou
closed
7 months ago
2
package import declaration not work?
#257
YikeZhou
closed
7 months ago
3
Issue with $clog2 of a parameter
#256
flaviens
closed
7 months ago
3
name conflict
#255
forthyen
closed
7 months ago
4
'parameter type' refers to wrong type
#254
elementary-particle
closed
9 months ago
3
[feature request] support for field name preservation when struct conversion
#253
Dragon-Git
opened
10 months ago
6
False incompatible bus size error on output and reg
#252
stitchlibar
closed
10 months ago
9
using interface arrays generates broken code
#251
tinebp
closed
10 months ago
13
ifndef and define behavior not compatible with Verilog
#250
stitchlibar
closed
11 months ago
5
sv2v: unexpected non-var or non-port function decl
#249
gadfort
closed
11 months ago
2
`parameter type`s for `interface`s not working with types that have been defined using `typedef`
#248
fl4shk
closed
11 months ago
4
Issues with newest iverilog
#247
dwRchyngqxs
closed
11 months ago
3
Struct parameters in module definition
#246
lpawelcz
closed
11 months ago
6
error: warning: passing 'char *' to parameter of type 'const unsigned char *' converts between pointers to integer types where one is of the unique plain 'char' type and the other is not [-Wpointer-sign]
#245
yurivict
closed
1 year ago
4
Print blocked statement to avoid dangling else even when it would be parsed correctly
#244
dwRchyngqxs
closed
1 year ago
2
Feature request: Documentation for contributing and writing tests
#243
dwRchyngqxs
closed
11 months ago
1
newest iverilog crashes when running tests
#242
dwRchyngqxs
closed
1 year ago
4
Make test prints a lot of warnings
#241
dwRchyngqxs
closed
1 year ago
2
Problems building
#240
philn128
closed
1 year ago
3
Generate region standard compliance fixes
#239
dwRchyngqxs
opened
1 year ago
6
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