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Every run with this action will produce some deprecation warnings. It needs to switch to node 16: [See](https://github.blog/changelog/2022-09-22-github-actions-all-actions-will-begin-running-on-node16…
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### Is there an existing CVA6 bug for this?
- [x] I have searched the existing bug issues
### Bug Description
I am trying to synthesize the CVA6 core using open-source tools. Our synthesis flow inv…
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I'm trying to run PPO2 on the 'Breakout-ram-v0' environment, but am getting a few errors. The command I am using to run the program is:
```python -m baselines.run --alg=ppo2 --env=Breakout-ramNoFra…
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Spun out from #9391. We want to check how synthesis tools treat casts from a logic vector to an enum variable of the same size, e.g.:
```systemverilog
parameter int MuBi4Width = 4;
typedef enum…
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hello,
Just a query on is there any possible way for having a "**runset**" for ICV and other files needed for physical layouting and verification on synopsys tools.
can it be generated?
or is …
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Hello,
I am writing to make a inquiry about supporting of another Ethernet adapter instead of using Intel cards.
When it comes to OpenAvnu, it apparently provides an example of Intel's IP driver s…
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## Observed Behavior
[compile_tb_stdstreams.log](https://github.com/user-attachments/files/16634707/compile_tb_stdstreams.log)
## Expected Behavior
## Steps to reproduce the issue
…
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**BOOM version:**https://github.com/riscv-boom/riscv-boom/tree/779c62c5634847b517be64c554af66829de40067
**Process:**SMIC 40nm
**Detail description:**
Using design compiler of synopsys,I only …
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I'm very interested in ghdl_ls there are however some starting hurdles that I've got to overcome.
**1. How does a project have to be setup for multiple libraries (not only work). Multiple sections?…
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Is there a reason the usb module is disabled for stm32f105 series MCUs? The datasheet says it supports USB OTG FS.
```
#[cfg(all(
feature = "stm32-usbd",
any(feature = "stm32f102", feature…