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We currently see these warnings during Vivado compilation. I'll put these here in case others have time track them down.
`WARNING: [Synth 8-7032] RAM "genblk1[1].mem_reg" have possible Byte Write p…
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**Issue by [bjharper](https://github.com/bjharper)**
_Sun Sep 3 03:34:00 2017_
_Originally opened as https://github.com/machinekit/machinekit/issues/1269_
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I have had some success compiling an…
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If I've understood correctly, @sbourdeauducq believes that we will have issues with the AMC WR implementation, even if both DDMTD inputs are from IOs in the same bank as the helper PLL. This is a prob…
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Using the HMC7043 cycle slip feature intermittently causes breakage of the DAC synchronization, which is manifested by a 53.33ns slip between the two DAC chip outputs.
The magnitude of the slip is …
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Hi,
I am integrating our IP into SDAccel Environment. What I have done are inside IPI GUI. I have checked "Use Auxiliary (non-AXI) Signal Ports" in "Enable IP Interface" tab inside VIVADO. Also I con…
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I've started sketching out requirements for a fast DAC to be used for ion shuttling/splitting. It's on the [Wiki](https://github.com/m-labs/sinara/wiki/Shuttler).
All comments welcome...
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Mechanical:
- [ ] SMA connector clearance with PCB edge - move it 100um outside
- [ ] Align J6, J7
- [ ] adjust 4-th upper panel SMA hole
- [ ] move T7 away from the board edge
- [ ] J16, J18, J…
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Hello,
Not sure, since there are no forums: I'm trying to synthesize it for an FPGA Xilinx xcvu9p* family, I created a design block that connects the three AXI, to access brams, the goal it is ev…
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Building .bit from source using
```
commit 440e19b8f9c8ebfce80402a519796cee7fdd6b06
```
I see...
```
$ flterm /dev/ttyUSB2
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