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**Issue by [Fatsie](https://github.com/Fatsie)**
_Saturday Nov 16, 2019 at 13:21 GMT_
_Originally opened as https://github.com/m-labs/nmigen/pull/270_
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I am using nmigen for generating RTL to b…
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Thank you for the details on the previous issue I opened.
I have pulled the [latest commit](https://github.com/alchitry/Alchitry-Labs-V2/commit/08d1d6b340a8cf31a9976443dcfad2130582d600) you have a…
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Tried this in release 3.7 on Ultimate II, 3.10a on Ultimate 64 Elite and 3.10e on Ultimate II+L:
Using Commodore MPS, Epson FX-80/JX-80, IBM Graphics or IBM Proprinter emulations, once a printed li…
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Right now, the scope of formal is the following, copied directly from IRC:
>(11:56:43 AM) whitequark: the entire scope of formal verification in nmigen at the moment is "it can generate verilog or …
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### Description
This is a bucket-issue for improving Questa support in OpenTitan.
> I want to use this issue to drive support forwards by gathering user feedback into a working branch of fixes, …
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needed for definition of done. creating an issue for tracking
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The goal is to both:
* Make it easier for all people discovering SpinalHDL (knowing VHDL and Verilog might help but it is not a requirement)
* Make it easier for people to find information
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This is an inquiry to the wider audience who are working on getting NVDLA running on a FPGA platform--we'd like to share what we are doing and check progress on other groups out there .
we are putt…
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Hello Nunobrum,
I am not sure if this is the right place for a request like these so apologies in advance if this is the wrong place.
I have been very much enjoying running Qspice in batch modes…
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Hello and thank you very much for sharing your knowledge !
Based on your source code, I am currently implementing a new version of the verilog that controls the backlight, generating a variable PWM s…