riscv riscv-fast-interrupt issues

riscv / riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

https://jira.riscv.org/browse/RVG-63

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issues

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MNXTI CSR clarifications?

#433 mark-honman opened 1 week ago
0
Clarify which CLIC CSRs are accessible in non-CLIC mode

#432 mark-honman opened 1 week ago
0
414 move register layout definitions into wavedrom

#431 wmat opened 1 week ago
0
Improve description of software examples

#430 mark-honman opened 2 weeks ago
1
Clarification of roles of MTVEC and MTVT

#429 mark-honman opened 2 weeks ago
0
Debug entry during hardware vectoring.

#428 MarkHillCodasip opened 1 month ago
0
Spec doesn't say to clear the second lowest bit of trap handler addresses

#427 Timmmm opened 1 month ago
0
In Appendix, we should not have CLIC interrupt ID recommendation chapter.

#426 jb-brelot-nxp opened 1 month ago
0
Does CLIC spec need to be re-organized to integrate into Priv ISA manual?

#425 james-ball-qualcomm closed 1 month ago
0
clicintattr.mode should not be writable from S-mode

#424 christian-herber-nxp opened 1 month ago
1
James ball clic issue 411

#423 christian-herber-nxp closed 1 month ago
1
Scratch Swap CSR (sscratchcswl) CSR section missing in ssclic chapter

#422 james-ball-qualcomm opened 1 month ago
0
The smclicshv extension naming (i.e. sm*) suggests it only has M-mode features but it affects S-mode and has one S-mode CSR bit

#421 james-ball-qualcomm opened 1 month ago
4
Recommend moving definition of indirect CSRs into their own chapter and clarifying they are accessed via M-mode or S-mode CSRs.

#420 james-ball-qualcomm opened 1 month ago
2
James ball clic issue 409

#419 james-ball-qualcomm closed 1 month ago
7
Inconsistency on which fields are zeroed when switching to CLINT mode

#418 Timmmm opened 1 month ago
0
issue #411 - Clarify that smclicshv ignores 1 or 2 LSBs of vector table entry (depending on IALIGN)

#417 james-ball-qualcomm closed 1 month ago
3
Simplify and fully specify xscratchcsw[l]

#416 Timmmm opened 1 month ago
0
Write side-effects for csrrs rd, mnxti, rs1 when rs1 is not x0

#415 MarkHillCodasip opened 2 months ago
1
Move register layout definitions into wavedrom

#414 christian-herber-nxp opened 2 months ago
6
Make Ssclic mandatory if smclic is implemented and S mode is implemented.

#413 jb-brelot-nxp closed 1 month ago
2
Explicitly list dependence on Smcsrind/Sscsrind

#412 christian-herber-nxp opened 2 months ago
0
smclicshv psuedo-code assumes hart has IALIGN=16 and needs to be better documented

#411 james-ball-qualcomm closed 1 month ago
5
Should we make the smclicshv (Selective Hardware Vectoring) extension mandatory in CLIC 1.0?

#410 james-ball-qualcomm closed 1 month ago
5
Smclic section contains a lot of changes relevant only to S-mode

#409 christian-herber-nxp closed 1 month ago
8
Improved clarity regarding xcause when switching between CLIC and CLINT

#408 christian-herber-nxp closed 2 months ago
1
The text definition of `xscratchcswl` is incomplete

#407 Timmmm opened 2 months ago
1
xscratchcswl privilege behaviour not fully specified

#406 Timmmm opened 2 months ago
2
Conflicting statements about switching from CLIC to CLINT

#405 Timmmm closed 2 months ago
2
Make some reorganizations in the chapter.

#404 jb-brelot-nxp closed 2 months ago
3
issue #401 - First round of changes to improve clarity of document. Removed mention of U-mode interrupts.

#403 james-ball-qualcomm closed 2 months ago
4
Clarify behaviour of xnxti register version in smclicshv

#402 jakubahh opened 2 months ago
1
Many (93) comments in attached PDF of latest CLIC spec

#401 james-ball-qualcomm closed 1 month ago
3
Make shv a per level property

#400 christian-herber-nxp opened 3 months ago
1
an exception trap on the trap handler function address fetch cannot return to the instruction interrupted (smclicshv)

#399 hirooih opened 4 months ago
0
Questions on Release 0.9

#398 hirooih opened 4 months ago
0
Revremark and revnumber are inconsistent

#397 christian-herber-nxp closed 3 months ago
0
Missing a catchy terminology for the selection priority

#396 christian-herber-nxp opened 6 months ago
6
mnxti pseudo code clarification when rs1 == x0

#395 dansmathers opened 7 months ago
0
Fix general interrupt overview table ie description

#394 dansmathers opened 7 months ago
0
for issue #391 - assignment of miselect/siselect range for CLIC

#393 dansmathers closed 8 months ago
0
add recommended layout if mem-mapped access to CLIC regs is supported

#392 dansmathers closed 1 month ago
1
Tentative assignment of base value of miselect/siselect for CLIC

#391 dansmathers closed 8 months ago
2
For issue #385 - clarify WARL for clicintctl/clicintattr

#390 dansmathers closed 8 months ago
0
For issue #388 - fix miselect/siselect values of clicintctl/clicintattr

#389 dansmathers closed 8 months ago
0
clicintctl/clicintattr miselect offsets are incorrect

#388 dansmathers closed 8 months ago
1
clarify indirect CSR text for issue #377

#387 dansmathers closed 8 months ago
0
rename title m-mode indirect CSR access

#386 dansmathers closed 8 months ago
0
Allow fixed configuration for some fields

#385 christian-herber-nxp closed 8 months ago
5
revert #370 merge - nxti will again not return shv interrupts

#384 dansmathers closed 8 months ago
0