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With the newest repo, including rocket-chip, bbl and linux (actually I use the `priv-1.9` branch), I can run linux over the rocketchip FPGA implementation without FPU. But when I run the STREAM bench…
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Hello zscale-developers,
could you provide some additional information, how to convert the scala sources to verilog? Adding the following main in zscale.scala results in Chisel. ParameterUndefinedExce…
michg updated
7 years ago
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Here's my Chisel code:
``` scala
val h_table = SeqMem(num_entries, Vec(fetch_width, Bool()))
...
val waddr = hwq.io.deq.bits.index …
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I'm porting fpga-zynq to the Digilent PYNQ-Z1 board ([my fork](https://github.com/GuzTech/fpga-zynq)) for which I used the Zybo as a reference. The problem is that when I run the `fesvr-zynq pk hello`…
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This is essentially reopening #308, albeit with a different proposed solution. We'd like to split out the generation of the verilog testharness with that of the actual DUT to enable gate-level simula…
ben-k updated
7 years ago
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Hello,
I'm fairly new to the RISC/Rocketchip architecture and I'm trying to get the test program running on a couple of Zynq boards. I'm able to go through all of the steps in the guide expect getting…
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I'm cloning a clean copy of the rocket-chip repo, building the tools from scratch, and changing Chisel version in ./Makefrag to `CHISEL_VERSION ?= 2`.
Steps to reproduce:
``` bash
git clone https://…
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I want to build a C emulator that is capable of generating VCD waveform, so I enter the directory of emulator and compile with "make debug". Then I find the an error (gcc version is 5.3.1 20160413, OS…
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Recently, I find that rocket-chip generator is unable to generate verilog code for boom core, and I am suspecting that it is caused by the undefined macro $(ROCKETCHIP_ADDONS) in /rocket-chip/Makefrag…
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