-
As title,
I did some research and found that .py is python files, however, since I am new to python, have no idea how to use it.
BTW, I already used vivado and generated .bit file.
And I am g…
-
Here is my bug when building the mnist folder on vitis_hls 2022.2
-
I am trying to buuild `zcu102_pl_ddr_stream` platform but I am getting following error, while I can make `zcu102_base` platform without any problem. I wondering what can be the cause of the problem.
…
-
2017-12-14
论文学习：
paper《In-Datacenter Performance Analysis of a Tensor Processing Unit-2017》
专利《Prefetching Weights for a Neural Network Processor》
NVDLAonFPGA
1.安装完成Vivado2017.1，windows版本加入…
-
Equipo 2
-
Hi @dsumorok ,
Could you please explain to me how did you create the rsEncoderWrapper/ rsDecoderWrapper IP blocks?
Thank you
-
Hi,
I am following the below steps:
1) git clone git@github.com:antmicro/alkali-csd-projects.git
2) git submodule update --init --recursive
3) docker pull antmicro/alkali or make docker
4) D…
-
Hi, I've finished all the steps in HLS and Vivado. But when i launch the xilinx SDK and start to debug the C project "zynqnet_sdk" which has a main() in cpu_top.cpp, the xilinx SDK tells me "Launch Fa…
-
Ran make nexys4_ddr_rocket with Vivado 2018.3
and have ERRORs
any hint ?
WARNING: [filemgmt 56-315] Source scanning failed during design analysis. To get more details run synthesis or simulation …
-
I am not sure if it applies to all tools, but for Vivado FuseSoc does not use any parallelism capabilities (Vivado `-jobs` parameter).
I wanted to improve this, so I have added support in Edalize htt…
m-kru updated
3 years ago