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**Summary**
The SV `nettype` keyword is currently not supported by Verible.
Since analog circuit models may sometimes contain this keyword, it would be nice if this was supported as well.
**Tes…
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Prevent breakages of Kythe extraction logic by running the [verification tests](https://kythe.io/docs/kythe-verifier.html) as a part of Verible's continuous integration.
The initial set of Kythe ve…
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The following error is causing Verbile to not build on Ubuntu Xenial;
```
/usr/include/c++/5/ext/new_allocator.h:120:4: error: no matching function for call to 'std::pair::pair(absl::lts_2020_09_23:…
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Verible (thankfully) renamed their binaries to include "verible" in the name. We need to follow in the verible lint and format backends.
https://github.com/google/verible/commit/a6d36642f30bacefef…
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## Input test case
```systemverilog
`include`d
```
## Describe what is wrong or missing
Crashes:
```
Crash Type: CHECK failure
Crash Address:
Crash State:
symbol.Kind() == SymbolKi…
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I don't know much about how dependabot works -- any idea what might be wrong here? I don't see any opened or closed pull requests from it for slang for several weeks.
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## Input test case
(not reduced, direct from fuzz-testing report)
[clusterfuzz-testcase-minimized-verilog_kythe_extractor_fuzzer-6216524817498112.txt](https://github.com/google/verible/files/523…
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**Test case**
```systemverilog
module alert_handler_esc_timer_fpv import alert_pkg::*; (
// i/o ports
);
```
**Actual output**
```systemverilog
module alert_handler_esc_timer_fpv
im…
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Some style guides recommend prefixing all generate block labels in a design with an identifier like `g_*` or `gen_*`. Hence, a Verible lint rule that can check for such patterns in generate labels wou…
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**Describe the bug**
`verilble-verilog-syntax` crash on these two files and give `"E(node.Tag().tag) == expected_node_enum (kFunctionCall vs. kReference)`.
**To Reproduce**
run `verible-veril…