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tl;dr: Print out GCC/LLVM-style to pretty-print error information with the failing line and a carat to the failing column.
### Checklist
- [x] Did you write out a description of the feature you …
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For now, there's no way to express readwrite ports in Chisel3. In Chisel2, they are inferred from read and write ports by checking their enable signals. I think there should be an explicit way as well…
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A:
```mlir
firrtl.circuit "Top" {
firrtl.module private @Bar(out %b: !firrtl.uint) {
%0 = firrtl.wire : !firrtl.uint
%c1_ui1 = firrtl.constant 1 : !firrtl.uint
firrtl.str…
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### Describe the bug
I am not able to run tree-sitter as it shows hoon and gdscript can't be installed. I have a windows PC. Moreover the makefile in the hoon and gdscript doesn't works
![image]…
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**Type of issue**: feature request
Related issues:
https://github.com/freechipsproject/firrtl/issues/508
https://github.com/freechipsproject/firrtl/pull/530
**Impact**: API addition (n…
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### Describe the bug
The parser fails to identify discrete parameter declarations and it combines them under a single one. This behavior only occurs in unnamed parameters and when using the language …
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Hi!
I am currently working on reimplementing the rfuzz passes in yosys to make it compatible with some other tools I am working with. I have realised that the width of the coverage port does not ma…
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Hello!
I am trying to apply RFUZZ to a design generated by Chisel. When passing the corresponding .fir file, I encounter the following errors:
`line 1984:39 mismatched input ':' expecting {'.', '[…
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Recently I have been doing work to adapt XiangShan project to CIRCT.
I have encountered the following assertion failed when compiling XiangShan using
Chisel 3.5.0
chisel-circt 0.8.0
CIRCT 1.37…
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**Type of issue**: bug report
**Impact**: unknown
**Development Phase**: request
**What is the current behavior?**
The following chisel test
```scala
class IntervalInferenceTester exte…