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Hi,
We have a set up to phase lock two IR laser heads using a RedPitaya. However, for experimental reasons, we need to lock them using green beams produced by SHG on both IR laser. The SHG are insi…
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Hi,
I'm using the latest stable version of the Pulpissimo (tag v7.0.0: https://github.com/pulp-platform/pulpissimo/tree/v7.0.0), with the Ibex core, running on the Zedboard.
I'm currently tryin…
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Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will …
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We're experiencing an issue that's having us tearing our hair out a little bit, in which the TCP connection between the koheron server and a computer seems to stall.
We've got a computer connected …
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```
# cd /lib/firmware; echo system_top.bit.bin > /sys/class/fpga_manager/fpga0/firmware
# echo 79024000.cf-ad9361-dds-core-lpc > /sys/bus/platform/drivers/cf_axi_dds/unbind
# echo 79020000.cf-ad93…
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The PRs from @xuminready has been merged which updates the source but no [new releases](https://github.com/parallella/parabuntu/releases) were published.
There is a [forum thread](http://parallella…
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### LUT---Look Up Table
查找表是最FPGA中实现逻辑的基本单元,通常有4输入查找表和6输入查找表(4/6 input LUT)。
以4输入查找表为例,可以看成4位地址输入,1位数据输出的存储器,存储的内容是真值表,依照输入的地址的真值输出对应的数据。
LUT是组合的,如果RTL是时序电路,则实际上是LUT+FF组成。
LUT就是一个4/6地址为的RAM。
Q:为…
cisen updated
2 years ago
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I just left PR #1 to start this effort.
My ultimate target (I would love to hear your feedback) is to be able to reuse old ESP8266-01 for JTAG programming via WiFi. I don't want to store any bitstrea…
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similar to https://github.com/olofk/serv/issues/83 in WSL, the Windows version of `fusesoc` seems to not properly detect which version of python to use.
Here in Windows, `python` is Python versio…
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Hello,
I am afraid that we are doing the exactly the same thing.
https://github.com/Nic30/hwt
https://github.com/Nic30/hwtLib/blob/master/hwtLib/samples/showcase0.py
This library is also S…
Nic30 updated
5 years ago