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Issue raised on call with Creotech on 12/18. "RF output has correct frequency but every second channel has 2x amplitude." @marmeladapk says this might be due to error in BaseMod configuration.
@sb…
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Does Migen support [reduction operators](https://www.nandland.com/verilog/examples/example-reduction-operators.html)? If not, is there a concise way to express them with Python?
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# Bug Report
## One-Line Summary
The command line switches to select an `Experiment` from a file are inconsistent.
## Issue Details
### Steps to Reproduce
`artiq_run`: `-e EXPERIMENT, -…
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@wizath my fuzzing just stalled while waiting for a response from Booster.
Looking at the logstash I see nothing:
```
> i2cerr
#0 #1 #2 #3 #4 #5 #6 #7
I2C ERR 0 0 0 0 0 0 0 0
>
> i2cdete…
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The jitter on the SYNC_IN signal from Kasli to the AD9910 (throught the LVDS buffers and the fanout) is very high in some caes (the tester setup connected to the buildbot).
At validation delay 1 …
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* symptom: no link at transceiver level (no comma alignment)
* efd735a6ab3d2c4b1493fd2e032559d2c1bd525d does not have the bug, current master has it
* reverting high-resolution TTL clocking changes …
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Why AC-couple it? Having a well-defined DC level at the clock buffer input would help to avoid oscillations (the Si5324 can be shutdown from software giving a logic low at the input, so won't oscillat…
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I receive an error
```
[ 8.289000s] ERROR(board_artiq::hmc830_7043::hmc7043): invalid HMC7043 ID: 0x00000000
panic at src/libcore/result.rs:945:5: cannot initialize HMC830/7043: "invalid HMC…
vmsch updated
5 years ago
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- Some builds give no output at all on the UART
- When I've seen this, I've found that repeatedly building/flashing the same version of the code reproducibly gives no output on the UART. I can switch…
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Idea gleaned from http://lists.llvm.org/pipermail/llvm-dev/2017-April/112026.html.