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Hi,
Running synthesis with Vivado 2022.1 I get the following error log:
```
WARNING: [Synth 8-9887] parameter declaration becomes local in 'ip_mux' with formal parameter declaration list [/sour…
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Currently in `clash-testsuite` we allow testing against `modelsim` for SystemVerilog only. However, we could allow testing against _all_ HDL supported by Clash in `modelsim`, which would help identify…
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I'm not able to compile the file "sim_waveform.vhdl" using Vivado (Version 2015.2).
I get the following errors:
```
ERROR: [VRFC 10-925] indexed name is not a time [/home/albert/git/dnk7/src/hw/PoC/s…
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Hola, estoy intentando usar Vivado en mi computador personal y tengo el siguiente Warning (porque ni si quiera es error):
[filemgmt 56-2] IPUserFilesDir: Could not find the directory 'D:/Universida…
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Hi,
I'm using Linux Mint 18 Sarah. I'm also using the Xilinx Vivado IDE, which looks like this after installing Infinality. Note that the IDE comes with its own JRE.
![xilinx-jre](https://cloud.…
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What is the correct procedure to increase the block ram in lowrisc version 0.2 to run large bare metal applications?
I changed `localparam BRAM_ADDR_WIDTH = 16;` to `localparam BRAM_ADDR_WIDTH = 17;`…
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I have the log2 function defined in a separate "functions.sv" file which is then included in the "config.sv" file only. The "functions.sv" file is not added to the synthesis project but the "config.sv…
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Hello! I'm using PYNQ-Z2, vivado 2020.1, and I want to generate a image resize IP with resize.tcl. But when I run it, an error occurred:
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_rd_socket…
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Quick Summary
Attempting to convert a trained Keras Model with Quartus as Backend. but get this error
![error](https://github.com/fastmachinelearning/hls4ml/assets/47188943/e99da77e-ee5c-48af-b9c9-…
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When trying to add the _cl_wrapper_ module, I get an _Incompatible Module_ issue that prevents me from adding it. I also see that _obuf_, _pe_, _banked_ram_, _obuf_mem_wrapper_, _mux_n_1_, _signed_add…