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In 'Profiling the Application' of section create my first SDAccel program - The SDAccel.ini has been replaced by the xrt.ini file **SDx 2019** ( [https://www.xilinx.com/support/documentation/sw_manual…
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Right now neither rustc nor cargo are being installed as part of the SDK build - this would probably be quite useful, especially for cross-compiling projects with mixed C/Rust environments.
I made …
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Dear all,
what would be needed to add support for Xilinx Virtex 6 series of FPGAs?
I guess the reason that there is no support so far is mainly due to the fact that there was no demand. Or are t…
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Hi all, I'm getting Bus error when executing xdputil status and can't solve it.
Vitis AI version: Vitis AI 2.0
vivado & Petalinux version: 2021.2
SOM: MERCURY XU8 ( ZYNQ MPSOC ZCU7EV)
I'm work…
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See also #855 for issues
Good descriptions and flow template for PRs.
* Issue link.
* 1-2 lines: Why was the work done?
* bullets: Description of what work was done.
* Summary of testing done…
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When we use the JTAG programmer to download the fpga.bit file to the Alveo u50, the server will automatically restart. After restarting, the lspci will not be able to locate the board, and the blue li…
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Currently, some bare-metal tests have issues running on the Xilinx Virtex Utralscale+ board. We have to debug these issues using Vivado's post-synth simulation and add compatibility tests to our regre…
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I am trying the profiler on the resnet50 example running on the VCK190 board.
The board is loaded with the DPU reference design (https://github.com/Xilinx/Vitis-AI/tree/3.0/dpu). Vitis-AI runtime 3…
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For our new design, based on Xilinx Zynq SoC, we plan to use an Ethernet switch KSZ9477. We use Xilinx PetaLinux 2020.1 that comes with the kernel version 5.4.
We did preliminary testing on EVB-KSZ…
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Hi,
We have a custom Ultrascale+ MPSoC device with a Debian derived OS. Unfortunately, the VAI 3.0 User Guide and older versions of it only contain a build guide for Petalinux ([link](https://docs.…