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Hello, I would like to reproduce the fpgaDDS on the Xilinx kria26 series development board, can you provide some implementation details.
Thank you!
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Hi guys, this is probably not an issue but something I'm missing, I'm sure.
Consider this:
``` Haskell
markAuthFail :: AuthUser
-> Handler b (AuthManager b) (Either AuthFailure AuthUser)…
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I have a websocket client based on websocketpp downloaded from BTCC.com, and I would like to receive trading data with this solution.
The client is able to start and receive messages, but it always g…
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Hello,
I see that doing this kind of loop, the free heap decreases **if** an internet loss occurs in the ssl handshake step.
After a few disconnections, this ends up in a device that can never aga…
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I have tried to fixed the "OPMODE Input Warning" . And this warning sames coming for "fpga_top_fadd_32ng8j.v" alone, which adds two floating data (32bit) using DSP48E. Other files including "fixed-po…
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BiGG provide a very handy universal model at : http://bigg.ucsd.edu/data_access
The JSON format is supposed to be a COBRA-compliant model, however it does not respect the schema from : https://github…
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https://cloudplayer99.github.io/2020/06/18/%E5%8F%AA%E9%9C%80xx%E5%85%83%EF%BC%8C%E4%B8%80%E5%91%A8%E5%AD%A6%E4%BC%9AVerilog%20HDL%EF%BC%8C%E7%9C%8B%E5%88%B0%E8%B5%9A%E5%88%B0%20+qq%20%E5%B0%B1%E8%83%…
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> **Describe the bug**
It looks like if I set up a task with the following in the config/task.conf:
```
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verifica…
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Setting both EN_HLS=1 and EN_PR=1 leads to a synthesis issue.
Steps to reproduce for Alveo U200 (but I guess it does not work on any platform):
```sh
cd hw
mkdir build
cd build
cmake .. -DFDEV…
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I would like to know why adalm-pluto is not supported? Not only openbts, but also others such as srslte
What makes it not supported? Is it some kind of API or command interface that only the more exp…