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https://vvviy.github.io/2018/09/12/nv_small-FPGA-Mapping-Workflow-I/
Keep self busy.
VVViy updated
2 years ago
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This issue concerns the branch to resolve issue 196: https://github.com/Xilinx/ACCL/tree/196-reduceallreduce-issues-on-cyt_rdma
Gather sometimes switches up the output of the first rank and the sec…
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Not sure where else to put this, but I was actually interested in this exact same concept, and there isn't really anything on the 'net about this. Do you have any interest in working on this project?
…
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Hello,
I followed the wiki (https://github.com/cambridgehackers/zedboard_manifests/wiki/ZedboardAndroid4.1).
When I build, the first error that comes is:
find: 'src': no such file or directory
after…
ghost updated
9 years ago
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# FPGAs Are Magic I
> Any sufficiently advanced technology is indistinguishable from magic.
> - Arthur C. Clark
FPGAs are *magic*.
On my Twitter account, I have been posting diagrams of the …
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when i boot from SD with debian written in , it will enter emergency mode. what i used is genesys2_ariane_xilinx.new.mcs and rootfs.tar.xz download from https://github.com/lowRISC/lowrisc-chip/…
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I got a blocking issue when running XDMA driver on my ARM platform: N1SDP.
On the U280, I generated one FPGA project with XDMA:
![image](https://github.com/Xilinx/dma_ip_drivers/assets/16829846/d4…
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Hello! Thank you for this wonderful project, Mr. Tarassov.
I wish to add a CAN peripheral. Would you recommend doing this using the provided [Vivado CANFD IP](https://www.xilinx.com/products/intel…
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https://github.com/MPSU/FPGA_pract/blame/853e9e466576adacb3134de7f0dcb15fb35ad1bc/Labs/01.%20Tcl/README.md#L58
Правильный путь:
>call D:\Xilinx\Vivado\2023.1\settings64.bat
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**Describe the bug**
After #883 i discover that neorv32 determines any printed character as "?".
Looks like #883 uart_rx upd broke something
**To Reproduce**
Check "sreg" bus of "rx_engine_t" re…