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**Mod version:** CTM_DEV-MC1.15.2-1.1.0.12
The game crashes to desktop with an IllegalArgumentException if the incorrect number of textures are provided. Personally I feel that resource loading sho…
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**Type of issue**: bug report | feature request | other enhancement
**If the current behavior is a bug, please provide the steps to reproduce the problem:**
I'm uncertain if this is somethin…
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**I am currently running**
- SpongeForge version: 1.12.2-2838-7.3.0
- Forge version: 1.12.2-14.23.5.2854
- Java version: 1.8.0_265
- Operating System: Windows 10
- Plugins/Mods: Minecraft, Mi…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/firesim)
- [X] Yes, I searched [prior issues](https://github.com/firesim/firesim/issues)
- [X] Yes…
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Hi everyone, I am a newbie in Chisel.
Does anyone has experience in that case, please help me?
Thank you so much for any kind helps.
My goal is to add a instruction detecting signal (in particula…
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All right, so, new plan for this: I'm going to refactor what's in `generate-coder-table.py` and put it into [a subfolder](https://github.com/davidskalinder/mpeds-coder/issues/127) so it can be run by …
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Not sure which mod git to post it to so I'm posting it in both. Game crashes when entering the void dimension from Voidaic Arcana. No other mods used besides necessary ones for TG and VA to work.
Tes…
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Most of configurations in RC is untested. Making RC almost impossible to accept RTL changes to new RV extension from community.
0. Currently Makefile-based testing decoupled Chisel elaboration, FI…
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Hi, I am trying to use already present hardware accelerator in Rocket chip. To use it I am doing the following step:
1. In freedom/rocket-chip/src/main/scala/coreplex/Config.scala adding this
class…
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**Type of issue**: bug report
**Impact**: FPGA Building
**Other information**
lore@Helium:~/src/rocket-chip/vsim$ make verilog CONFIG=DefaultFPGAConfig
mkdir -p /home/lore/src/rocket-ch…