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When following the [Symbiflow examples](https://symbiflow-examples.readthedocs.io/en/latest/index.html) step by step, it fails when attempting to [build the counter example for xc7](https://symbiflow-…
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**Is your feature request related to a problem? Please describe.**
During adder implementation, if yosys has to synthesise an adder as a hard-macro and then in OpenFPGA flow, this is implemented as L…
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The LUT value for the buf implementation is incorrect (its order reversed). I have attached the repacked eblif file (top.repacked.net) here.
.subckt frac_lut4_arith in[0]=u_cnt3.count_dffr_Q_D[6] l…
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Hello,
We are trying to build an example of counter.
TARGET="arty_35" make -C counter_test
But we are getting this error at final end, let us know if we can get help around it.
We followed t…
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When a cell in a Verilog library has a wide port with reversed bit indices (eg. `input A[0:3]` instead of `input A[3:0]`) then performing a round trip of a Verilog design through BLIF and back to Veri…
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I've installed the SymbiFlow toolchain as described [here](https://symbiflow-examples.readthedocs.io/en/latest/getting-symbiflow.html), but when I want to run the `counter_test` example, I get an erro…
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## Steps to reproduce the issue
I use the symbiflow to synthesize a verilog design. I get an assertion error during the second `synth_xilinx` command:
```
21.5.2. Executing ABC9_OPS pass (helper…
dnltz updated
3 years ago
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the error is :
Finish prepacking.
Using inter-cluster delay: 2.18008e-09
Packing with pin utilization targets: BLK-TL-CLBLL_L:1,1 BLK-TL-CLBLL_R:1,1 BLK-TL-CLBLM_L:1,1 BLK-TL-CLBLM_R:1,1 BLK-TL-BRA…
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As discussed on IRC, trying to build the xc7/counter_test example results in a failed assertion in yosys during synth with my build configuration. Below are the exact steps to (hopefully) reproduce th…
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#### Expected Behaviour
The packer packs all the nets in only one top level tile (named `TILE`), instead of using two of them, causing a `not enough resources` error.
#### Current Behaviour
…