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The irresistable draw of the MeCrisp family is the large installed base, and the promise that many of those implemented peripherals will also work on Mecrisp-Ice. The problem is that I do not know wh…
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I'm trying to run the KV260 platform creation tutorial and am seeing an error in step 3 when building the example vadd application. At the point where we build the vadd_system_hw_link.prj, and from w…
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This issue is to gather references which might be interesting to be added to the docs:
**GHDL: a libre VHDL simulator**
> FOSDEM2015
> 2015 Jan 31-Feb 1, Brussels
>
> Short presentation of GH…
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Hello,
In CycloneVSoC-examples/FPGA-hardware/DE1-SoC/FPGA_DMA/ghrd_top.v, line 335:
.axi_signals_aruser (pio_controlled_axi_signals[ARPROT_BASE+: ARPROT_SIZE]),
.axi_signals_…
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A [software solution for this was discussed some years ago in this forum](http://forums.nesdev.com/viewtopic.php?t=5826).
Btw recently [many NES implementations in FPGA](https://github.com/mist-devel…
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I have a CNN model. I used the hls4ml and all file and bitfile generated completely. Now I used the deployment code to implement on FPGA(ZCU104), the prediction output of FPGA is always Zero.
**Tot…
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### Bug Description
Segmentation Fault running Test Code - Mnist while calling Convolution 2D.
#### Reproduction Steps
1. Downloaded the requisite file from http://yann.lecun.com/exdb/mnist/
2. …
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I'm the proud owner of a Colorlight 75E hardware version 8.0. The connections from the FPGA to the connectors are not yet mapped.
I would like to create gateware that shows what ball of the FPGA go…
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Hi, I have a question about [host memory access](https://github.com/Xilinx/Vitis-Tutorials/tree/2022.1/Hardware_Acceleration/Feature_Tutorials/08-using-hostmem).
In common where Vitis xdma is sued,…
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Hi,
I'm enjoying working with Schema so far. I'm not sure if there's a better place to ask these questions, but can anybody help me with the 'right' way to validate these constraints in lists of obje…
ghost updated
10 years ago