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management gpio registers `reg_gpio_mode1` and `reg_gpio_mode0` don't have an affect in the value of gpio_in_core when floating.
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benchmark openrcx vs caliber. precision did this last time?
https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/656/files
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## SPICE Model refactoring
Is there any intent to refactor the PDK? I suggest to make this a priority before tinkering more with the PDK itself because I observed the following issues.
- The de…
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DFFRAM currently supports 1RW2R regfiles, which is common on many architectures including RISC-V. However, some architectures only support reading from one operand. For example, RISC-V compressed inst…
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The `CPERSQDIST` value is ` 0.0000394` for all metals. As well, the value seems to be too low. When compared with the capacitance extracted using extraction tools, the value seems to be off by 10x
Fo…
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DRC violations in GF018_5VGreen_SRAM_1P_256x8M8WM1 vs. documented rule in the design manual
## PL.12
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# Expected Behavior
The simulation of transient including the noise
# Actual Behavior
I am able to run the noise simulation to see the noise spectral density in Ngspice. But I can't run the tran…
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Sphinx (https://www.sphinx-doc.org/en/master/) is the used by a large number of the existing Python and open source EDA ecosystem (for example the [Amaranth's own documentation](https://amaranth-lang.…
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It would be to explicitly document the directories and files layout requirements for satisfying a tapeout project submission on efabless.com.
Even if the current directory structure in `caravel_use…
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The precheck jobs came up with the following failure:
```
{{FAILURE}} 3 Check(s) Failed: ['Klayout FEOL', 'Klayout BEOL', 'Klayout Offgrid'] !!!
```
See the logs on https://github.com/proppy/carav…