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**Description**
Definind a 2-dimension array constant whose dimensions are not power of two, the synthesized code is invalid.
**How to reproduce?**
Minimal example:
```vhd :file: ent.vhd
libr…
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By looking at the sources of this repo, it seems that the project is to generate artifacts for a wide range of platforms (both OSs and architectures). That's nice! However, I'm lacking some explanatio…
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It would be nice if the output of the synthesis could be written to a file instead of to stdout.
This cannot simply be achieved by redirecting the output of `ghdl --synth --out`, because the output…
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### Is your feature request related to a problem? Please describe.
There is no build available for ARM macs, and I’m having trouble building it myself.
The README in this repository makes it seem …
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**Description**
When trying to synthesize a large design into verilog I run into a GHDL crash. The design I am synthesizing is both complex and large. Synthesis up until the crash used about 85 GiB o…
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Currently, after installing you need to set the following environment values;
```
export PATH="$INSTALL_DIR/$FPGA_FAM/install/bin:$PATH";
source "$INSTALL_DIR/$FPGA_FAM/conda/etc/…
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Hi Everyone,
I am trying to build microwatt for the Radiona ULX3S. I run into an error during Yosys execution. Mind you, it works fine on my Basys3 board with Vivado.
Here is what I have tried t…
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Is there a means to blackbox modules in ghdl?
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## Information
**VIM version**
Vim8.2.12 or Neovim0.5.0
Operating System: Windows10
## What went wrong
Verilog regex to match the linter information is always wrong when it's on…
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This issue aims to discuss moving to LiteX Hub packages. It was already executed in symbiflow-examples, and PRs are open for fpga-perf-tool and [symbiflow-arch-defs](https://github.com/SymbiFlow/symbi…