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Hello together,
I don't see any progress in the development / extension of functions in the public repos. Where can I find the active repos where development is ongoing ?
Best regards
Damian
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**Type of issue**: bug report
**Impact**: new rtl
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I have a potential bug on SonicBoom. I did not try rocket, but this happens with top of the tree chipyard.
This sequence of assembly ins…
renau updated
2 years ago
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This issue aims to determine whether OP-TEE can run on RISC-V architecture and identify any boards that can be used for testing.
Objectives
Confirm if OP-TEE is compatible with RISC-V architec…
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Is it possible to modify the linker script on my project? I want to keep all machine mode and user mode functions separated in memory. I thought that I might can build the machine code and the user …
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Congrats on this great project!
I am currently in the process of deploying Keystone to the [CVA6 RISC-V CPU](https://github.com/openhwgroup/cva6).
The bootup process and kernel module loading p…
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I've successfully built Deno (1.32.3, 1.32.4 in progress) in qemu-user and run on HiFive Unmatched on [Arch Linux riscv64](https://archlinux.felixc.at).
Some tweaks I did:
- Use system `clang`, …
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Is anybody aware of any existing ports or plans to port Duktape to RISC-V architecture?
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Hi,
Have a look at the following project:
https://github.com/oaken-source/parabola-riscv64-bootstrap
also check out:
https://github.com/oaken-source/parabola-riscv64-bootstrap
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error log:
```
../../gdb/infrun.c:5300: internal-error: int finish_step_over(execution_control_state*): Assertion `ecs->event_thread->control.trap_expected' failed.
A problem internal to GDB has be…
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RISC-V is a new kind of CPU architecture that's free and open source, as well as pragmatically designed to be easy to learn yet powerful enough to be useful for real world projects. It's already well …