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I am interested in adding support for the Basys3 FPGA that uses the same exact fpga part as the Cmod A7-35 fpga.
I have added a file in fpga/basys3.xdc that has the fixed pin numbers. I have also a…
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**The nomination period for The TOC Chair is open.**
Individuals interested in running for this position or individuals interested to nominate others must record the nominations under this GitHub is…
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From https://github.com/cocotb/cocotb/pull/2902#discussion_r826594980.
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As commented with @oleg-nenashev after his *What's new in LibreCores CI?* talk at ORConf2019, I believe there is room for contribution between [ghdl/docker](https://github.com/ghdl/docker) and libreco…
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It would be nice to have a collection of https://colab.research.google.com/ that demonstrate usage of the conda-eda packages to perform basic EDA talks.
We could seed it with some of the examples b…
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The librecores CI has been failing for some time, we now have setup github actions. Should we remove librecores CI?
https://ci.librecores.org/job/Projects/job/OpenRISC/job/mor1kx/job/master/
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Same as https://github.com/openrisc/mor1kx/issues/86 but for marocchino. CC @stffrdhrn @nancy-chauhan
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Hi...
My question cab be a really silly one but there is no emulator directory anymore in this repo.... So how can I make those rv32 cores that you have in src/main/scala directory?
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Hi,
I am wondering why `system_root` and `cores_root` are distinct values. Shouldn't they be unified as one kind of "FuseSoC Catalogs".
Beside this I would suggest to extend those from file system d…
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What would you like added/supported?
We wanna use verilator in our(Chisel) GitHub CI. However verilator didn't provide a binary release.
May we assist you in trying to fix this yourself?
If upstr…