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Clarify, please, expected behaviour on access to reserved address space (0x0008-0x003F, 0x00C0-0x07FF) and for custom address space (0x0800-0x0FFF) in memory map:
1. Access fault or hardwired zero (w…
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Version v1.11.1 has a very short release notes blurb about the two most recent changes to the library, but actually incorporates a number of other pull requests, some of which added features, and at l…
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The RISC-V Privileged ISA allows a hypervisor or a host OS to have one endianness (little-endian or big-endian) while each guest VM may have the same or opposite endianness. The current IOMMU spec do…
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Consider a two-stage (hypervisor) translation where:
* Final VS-stage PTE has W=0
* Final G-stage PTE has U=0
A load to this page will take a guest-page fault.
A store to this page will take a p…
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Hi,
I am evaluating the Icicle kit, board Rev 1.0.
I flashed [release 2021-08](https://github.com/polarfire-soc/icicle-kit-reference-design/releases/tag/2021.08) (using FlashProExpress, directly f…
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"For illegal-instruction exceptions, stval must be written with the faulting instruction." We feel that this is burdensome to implement because of data dependent illegal instruction exceptions. One ne…
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Hello,
Just after loading the reference Design I am getting multiple warnings first. I just tried to ignore them and program the icicle kit with the reference design and then access the SRAM via th…
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Hi,
We are relying on the watchdog mechanism to have the board rebooted in case of system freeze (Linux in our case).
That feature used to work as expected on the HSS 0.99.26 (together with Refe…
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For #14343, we'd like to be able to configure the PMP via GDB. At a high level, GDB talks to OpenOCD, which talks to the debug module via JTAG.
For some reason, Attempting to set `pmpcfg[0-3]` gene…
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I'm trying to run _OpenPiton+Ariane_
I built it and programmed the FPGA successfully on _Genesys 2.0_ board, also for the _simple hello_world.c_ test it _passes_.
Running **RISCV Benchmark tests** g…