-
Is there a estimated time frame for zcu104 support?
Regards
Jack
-
我們按照影片範例執行，有時候不打密碼直接進入192.168.2.99(圖1)，但沒有出現xilinx的資料夾，有時候會無法進入(圖2)
[圖1]
![messageIm…
-
Hello,
I am trying to build your project but when I run the build_static_design.tcl, i get an error. Here is the error.
ERROR: [Common 17-69] Command failed: File 'c:/Users/xxxxxx/AppData/Roa…
-
Hello, thank you very much sharing your valuable materials. I have some experience using Vivado HLS but I am still a slow learner for Hardware/FPGA design.
I am trying to run these Verilog files wi…
-
Hello
I have a question about downloading the Reconfigurable Module. You used Bitstream_Part to download them. What is it? How can we have our own Bitstream_Part?
-
After migrating to PYNQ 3.0.0, _pynq.Overlay("bistream_name.bit")_ returns a key error when the underlying FPGA designs has the processing system IP located within a hierarchy. In the traceback below…
-
I'm stuck in step 4, specifically 4.2. When I run the command: `python3 app_cifar10_tf2_resnet18.py`, I get the following output:
```ResNet18 CNN (pre-trained with ImageNet Dataset) fine-tuned to C…
-
Hi dear all,
I try to implement picorv32 on PYNQ-Z1 using vivado 2019.2 I followed your instructions until Packaging an Overlay. **Testing the Tutorial Overlay** failed due to the same error mentio…
-
Traceback (most recent call last):
File "../keras-YOLOv3-model-set/tools/model_converter/convert.py", line 407, in
_main(parser.parse_args())
File "../keras-YOLOv3-model-set/tools/model_co…
CC-Hi updated
3 years ago
-
If we follow the guide in the jupyter notebook (slcan_demo.ipynb) as indicated the build will fail.
I have compiled the modules with the folowing steps:
Start from:
```
sudo -i
```
Starting wi…