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Hi,
I am trying to synthesize the code for EL2 and when i try to read in the file "el2_param.vh" as an include file,
i get error at the first line as the compiler is not able to understand the cod…
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simple_spi.v file not found
.vh files not found
uart_top not found
swerv_wrapper_dmi not found
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I was running some tests on SweRV and Whisper and compared them I found these logs
---
### log generated by SweRV-EL2
``` // Cycle : #inst 0 pc opcode reg=value ; mnemonic
…
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![image](https://user-images.githubusercontent.com/18757974/60381657-aff8e700-9a8a-11e9-9b59-fe46cd9aaa62.png)
I find that many implementations about riscv-debug modules don't even use ```dtmcs.dmi…
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We should integrate Google's AI Macro Placer into OpenROAD. https://github.com/google-research/circuit_training
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Hi,
I want to know what version of RISC-V Vector Extension that you implement in SweRV-ISS, thanks.
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Hi all,
I want to generate elf-gcc and linux-gcc to use.
elf-gcc (Newlib) is done with no errors.
But fail to build "**Installation (Linux)**" and "**Installation (Linux multilib)**" with the same …
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Does openOCD have a "verilog" target/driver for simulations?
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@RRozak adding #4018 is causing the verilator_ext_tests and specifically SweRV to fail. It has this:
```
for (int i=0; i
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Hi! Are there any reliable benchmarks I could use in Verilator for a research paper?
I have tried [VTR datasets](https://docs.verilogtorouting.org/en/stable/vtr/benchmarks/) and [EPFL ones](https:…