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`make gpio_defaults` run on a caravel_user_project can incorrectly handle some Verilog constant/literal patterns in `verilog/rtl/user_defines.v` because it assumes a 4-character hex value.
```veril…
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It would be good to make Verilog testing independent from commercial tools - Synopsys VCS. A potential solution would be to use verilator instead.
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- [x] Replace verilog backend with verilogAST
- [x] Replace metadata["verilog"] with concrete verilogAST definition
- [ ] Replace verilog definitions of coreir/corebit with verilogAST
- [ ] Linking…
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When exporting a subblock as verilog (requiring the user to be in the edit mode):
![afbeelding](https://user-images.githubusercontent.com/13208934/129747567-a5c9417b-3685-42cd-aeaa-295645470023.png)…
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sv-parser aims to be fully compliant with IEEE1800-2017 standard. But if someone wants to use this parser to parse Verilog 2001 file, which is subset of SystemVerilog, there is no need to collect all …
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A reference for a hardware description language might be a nice thing to have.
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I just realized that assignment of a larger width signal to a small width signal results in a silent truncation in Chisel. This is one of the worst issues in Verilog and modern synthesize tools should…
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RT
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On the ULX3S we have 'slow' USB 1.1 host. With this PMOD it should be possible to have USB2.0 at 480Mbit/s
Are there any examples for this USB board? Can the ULPI be used as a replacement PHY in othe…
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Nic30 updated
5 years ago