-
I'm starting a new thread as this is a separate topic, but this relates back to my comments about `t_class_forward` in #3870.
An implementation file for `ClsB` is missing a `VL_TO_STRING` definitio…
-
When I tried to run the benchmarking script on the Jetson Nano, I get the following Error:
```
jetson@jetson ~/jetson_benchmarks> sudo python3 benchmark.py --all --csv_file_path ./benchmark_csv/tx…
-
cococtb: master (4aee0a0895a36606f9263df9370405663f496d22)
Ubuntu 20.04.2 LTS on WSL2
simulator: Verilator 5.007 devel rev v5.006-7-g4a8cfe367
---
When `pytest.raises()` fails, it raises a `…
-
Hi, I am trying to compile CVC on debian bookworm (testing) by calling `make -f makefile.cvc64`.
At first it looks promising, but at the stage where the linker is invoked using
`ld --relocatable…
-
-
As SpinalHDL/SpinalHDL#1022 discussed, the VPI code would remain in simulation directory (such as simWorkspace) without updated while version bumped.
It's reasonable to add a guideline on how to de…
-
This Verilog code:
```
module top (y, wire1, wire2);
input wire [7:0] wire1;
input wire [7:0] wire2;
output wire [15:0] y;
wire signed [15:0] wire_merged;
…
-
### Current behavior
i'm using:
- osx 12.0.1
- node 16
- create-react-app
- craco
- cypress 9.5.0
- typescript
writing e2e tests with cypress, it's been fine for a few months, then at a ce…
-
Hello
How are you?
Thanks for contributing to this project.
I am going to use your repo on Jetson (JetPack 4.6.1)
The environment on the Jetson is:
Python 3.6.9
CUDA: 10.2
cuDNN: 8.2.1.32
Tens…
-
Verilator version: master fadc677
Currently, for **simulation time callbacks** (see IEEE 1800-2017 38.36.2) other than `cbAfterDelay`, Verilator ignores the _cb_data_p->time_ field, and they are re…