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First off thank you for the hard work, this software you have created is really great! The biggest issue i've come across is problems with merge axis. The first issue I've had has been with response…
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Hi,
Can the DRAM controller core be generated without a CPU inside?
I would like to have an external CPU that performs the initialization and calibration.
Thanks in advance.
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salam ostad.
in site haie k ba inke flash nistan vali b surate darsadi loading daran. kheiliam ziad shodan.chejuri kar mikonan???
aksaran ba hamin canvas kar mikonam.
baied midunam az hamun raveshe…
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### Is there an existing core-v-mcu bug for this?
- [X] I have searched the existing bug issues
### Bug Description
To do simulation using verilator and gtkwave
we are trying to "build verilator m…
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Dear IPBus developers,
I am working at the European Synchrotron (ESRF) in Grenoble, developing electronics for instrumentation and data acquisition systems. I had the opportunity to learn and use …
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In the current implementation the `user` signal in `Axi4StreamBundle` is defined to be `dataWidth * userWidth`:
https://github.com/SpinalHDL/SpinalHDL/blob/ef0063da38424830a5b29f188e3887e2b043cb75/…
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While working with @mikeurbach to finish the details of implementing memories as discussed in #543 I am faced with the issue of interfacing the RTL code generated with a more general design, specially…
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The Rx buffer address location within the FlashMsg[x] struct (RxAddr64bit) is never set.
Value should be set to Destination Address (such as from `u32 XFsbl_Qspi32Copy(u32 SrcAddress, PTRSIZE DestA…
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Thanks for sharing ,
I've tried in Vivado 2018.03 ,
by default run `generate.sh` , there's generation errors.
Could you help me for adapting your works on latest toolkit?
And, if you 're int…
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When I read the interrupt signal from /dev/xdma0_events_0, it stuck.
A look at the interrupt event file reveals the following error:
```
$cat /dev/xdma0_events_0
cat: /dev/xdma0_events_0: Protocol…